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isplsi 2128/a in-system programmable high density pld 2128_10 1 use isplsi 2128e for new designs lead- free package options available! features enhancements isplsi 2128a is fully form and function compatible to the isplsi 2128, with identical timing specifcations and packaging isplsi 2128a is built on an advanced 0.35 micron e 2 cmos technology high density programmable logic 6000 pld gates 128 i/o pins, eight dedicated inputs 128 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic high performance e 2 cmos technology f max = 100 mhz maximum operating frequency t pd = 10 ns propagation delay ttl compatible inputs and outputs electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power in-system programmable in-system programmable (isp) 5v only increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays complete programmable device can combine glue logic and structured designs enhanced pin locking capability three dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control to minimize switching noise flexible pin placement optimized global routing pool provides global interconnectivity lead-free package options functional block diagram global routing pool (grp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) clk 0 output routing pool (orp) output routing pool (orp) clk 1 clk 2 logic array glb dq dq dq dq 0139(9a)/2128 c7 c6 c5 c4 c3 c2 c1 c0 d3 d2 d1 d0 d7 d6 d5 d4 b4 b5 b6 b7 b0 b1 b2 b3 a0 a1 a2 a3 a4 a5 a6 a7 description the isplsi 2128 and 2128a are high density program- mable logic devices. the devices contains128 registers, 128 universal i/o pins, eight dedicated input pins, three dedicated clock input pins, two dedicated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2128 and 2128a feature 5v in- system programmability and in-system diagnostic capabilities. the isplsi 2128 and 2128a offer non- volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. the basic unit of logic on these devices is the generic logic block (glb). the glbs are labeled a0, a1 .. d7 (figure 1). there are a total of 32 glbs in the isplsi 2128 and 2128a devices. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. copyright ?2006 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com august 2006 select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 2 use isplsi 2128e for new designs functional block diagram figure 1. isplsi 2128/a functional block diagram global routing pool (grp) 0139(10a)/2128 megablock reset input bus d3 d2 d1 d0 d7 d6 d5 d4 output routing pool (orp) output routing pool (orp) i/o 127 i/o 126 i/o 125 i/o 124 i/o 123 i/o 122 i/o 121 i/o 120 i/o 119 i/o 118 i/o 117 i/o 116 i/o 115 i/o 114 i/o 113 i/o 112 i/o 111 i/o 110 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 i/o 103 i/o 102 i/o 101 i/o 100 i/o 99 i/o 98 i/o 97 i/o 96 sdi/in 7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool (orp) output routing pool (orp) input bus in 5 in 4 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 95 i/o 94 i/o 93 i/o 92 output routing pool (orp) output routing pool (orp) input bus clk 0 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 y0 y1 y2 in 2 in 3 b4 b5 b6 b7 b0 b1 b2 b3 output routing pool (orp) output routing pool (orp) a0 a1 a2 a3 a4 a5 a6 a7 ispen i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 0 i/o 1 i/o 2 i/o 3 goe 0 goe 1 clk 1 clk 2 input bus sclk/in 0 mode/in 1 sdo/in 6 generic logic blocks (glbs) the device also has 128 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by the two orps. each isplsi 2128 and 2128a device contains four megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2128 and 2128a devices are se- lected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 3 use isplsi 2128e for new designs absolute maximum ratings 1 supply voltage v cc ................................... -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition capacitance (t a =25 c, f=1.0 mhz) symbol table 2-0006/2128 c parameter clock capacitance 15 units typical test conditions 2 c 1 i/o and dedicated input capacitance pf v = 5.0v, v = 2.0v cc y 8 pf v = 5.0v, v = 2.0v cc i/o, in data retention specifications t a = 0c to + 70c t a = -40c to + 85c symbol table 2 - 0005/2128 v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 4.5 2.0 0 5.25 5.5 v cc +1 0.8 v v v v commercial industrial table 2-0008/2128 parameter data retention minimum maximum units erase/reprogram cycles 20 10,000 years cycles select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 4 use isplsi 2128e for new designs switching test conditions figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a input pulse levels table 2 - 0003/2000 input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 3ns 10% to 90% 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. dc electrical characteristics over recommended operating conditions test condition r1 r2 cl a 470 390 35pf b 390 35pf 470 390 35pf active high active low c 470 390 5pf 390 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a/2000 output load conditions (see figure 2) v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using eight 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and the thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2128 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in cc in il in il cc out clock il ih condition min. typ. max. units 3 2.4 0.4 10 -10 -150 -150 -200 v v a a a a ma ma cc a out 165 325 cc cc commercial industrial ? a 165 select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 5 use isplsi 2128e for new designs external timing parameters over recommended operating conditions t pd1 units -100 min. test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030b/2128-100 1 4 3 1 tsu2 + tco1 ( ) -80 min. max. max. description # 2 parameter a 1 data propagation delay, 4pt bypass, orp bypass 10.0 15.0 ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback 100 81.0 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass 0.0 ns t su2 9 glb reg. setup time before clock 8.0 ns t co2 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock 0.0 ns t r1 a 12 ext. reset pin to output delay ns t rw1 13 ext. reset pulse duration 6.5 ns t ptoeen b 14 product term oe, enable ns t ptoedis c 15 product term oe, disable ns t goeen b 16 global oe, enable ns t goedis c 17 global oe, disable ns t wh 18 external synchronous clock pulse duration, high 5.0 ns t wl 19 external synchronous clock pulse duration, low 5.0 ns 77.0 100 6.5 5.0 6.0 13.5 15.0 15.0 9.0 9.0 13.0 57.0 83.0 9.0 0.0 11.0 0.0 10.0 6.0 6.0 18.5 6.5 8.0 17.0 18.0 18.0 12.0 12.0 select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 6 use isplsi 2128e for new designs internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2- 0036c/2128-100 inputs units -100 min. -80 min. max. max. description # 2 parameter 20 input buffer delay 1.8 ns t din 21 dedicated input delay 4.4 ns t grp 22 grp delay 2.6 ns glb t 1ptxor 25 1 product term/xor path delay 8.0 ns t 20ptxor 26 20 product term/xor path delay 8.8 ns t xoradj 27 xor adjacent path delay 9.8 ns t gbp 28 glb register bypass delay 1.3 ns t gsu 29 glb register setup time befor clock 1.4 ns t gh 30 glb register hold time after clock 6.0 ns t gco 31 glb register clock to output delay 0.4 ns 3 t gro 32 glb register reset to output delay 1.6 ns t ptre 33 glb product term reset to register delay 8.6 ns t ptoe 34 glb product term output enable to i/o cell delay 9.0 ns t ptck 35 glb product term clock delay 5.6 10.2 ns orp t ob 38 output buffer delay 2.0 ns t sl 39 output slew limited delay adder 10.0 ns 0.5 2.2 grp 1.7 t 4ptbpc 23 4 product term bypass path delay 8.1 ns t 4ptbpr 24 4 product term bypass path delay 6.8 ns 6.8 7.3 8.0 0.5 5.8 5.8 1.2 4.0 0.3 1.3 6.1 8.6 4.1 7.1 t orp 36 orp delay 2.0 ns t orpbp 37 orp bypass delay 0.5 ns 1.4 0.4 outputs 1.6 10.0 t oen 40 i/o cell oe to output enabled 4.6 ns t odis 41 i/o cell oe to output disabled 4.6 ns 4.2 4.2 t goe 42 global output enable 7.4 ns 4.8 t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 2.7 3.6 3.6 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 2.7 3.6 3.6 ns clocks 2.7 2.7 t gr 45 global reset to glb 11.4 ns global reset 9.2 select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 7 use isplsi 2128e for new designs isplsi 2128/a timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25 - 27 #33 - 35 #43, 44 #36 reset ded. in #21 #20 #28 #29 - 32 #38, 39 goe0, 1 #42 #40, 41 0491 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock = = = = t su logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #35) (0.5 + 1.7 + 7.3) + (1.2) + (0.5 + 1.7 + 4.1) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20+ #22+ #35) + (#30) - (#20+ #22+ #26) (0.5 + 1.7 + 7.1) + ( 4.0) + (0.5 + 1.7 + 7.3) = = = = t co clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20+ #22+ #35) + (#31) + (#36 + #38) (0.5 + 1.7 + 7.1) + (0.3) + (1.4 + 1.6) 4.4 ns 3.8 ns 12.6 ns table 2-0042/2128 note: calculations are based upon timing specifications for the isplsi 2128/a-100l. select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 8 use isplsi 2128e for new designs power consumption power consumption in the isplsi 2128 and 2128a de- vices depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 4 shows the relationship between power and operating speed. 0127b/2128 i cc can be estimated for the isplsi 2128/a using the following equation: i cc (ma) = 20 + (# of pts * 0.48) + (# of nets * max freq * 0.009) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 100 200 300 0 20 40 60 80 100 f max (mhz) i cc (ma) notes: configuration of eight 16-bit counters typical current at 5v, 25 c isplsi 2128/a 250 150 figure 4. typical device power consumption vs fmax select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 9 use isplsi 2128e for new designs pin description 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability. dedicated clock inputs. these clock inputs are connected to one of the clock inputs of all the glbs on the device. active low (0) reset pin which resets all of the glb registers in the device. input - dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. input - this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi is also used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated input pin. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2-0002/2128 pqfp/mqfp pin numbers description 25, 32, 37, 42, 48, 54, 59, 65, 70, 76, 82, 87, 93, 106, 113, 118, 123, 129, 135, 140, 146, 152, 157, 3, 8, 15, 26, 33, 38, 43, 49, 55, 60, 66, 72, 77, 83, 88, 94, 108, 114, 119, 124, 130, 136, 141, 147, 153, 158, 4, 9, 16, 28, 34, 39, 44, 50, 56, 61, 67, 73, 78, 84, 89, 95, 109, 115, 120, 126, 132, 137, 142, 148, 154, 159, 5, 11, 17 i/o 0 - i/o 4 i/o 5 - i/o 9 i/o 10 - i/o 14 i/o 15 - i/o 19 i/o 20 - i/o 24 i/o 25 - i/o 29 i/o 30 - i/o 34 i/o 35 - i/o 39 i/o 40 - i/o 44 i/o 45 - i/o 49 i/o 50 - i/o 54 i/o 55 - i/o 59 i/o 60 - i/o 64 i/o 65 - i/o 69 i/o 70 - i/o 74 i/o 75 - i/o 79 i/o 80 - i/o 84 i/o 85 - i/o 89 i/o 90 - i/o 94 i/o 95 - i/o 99 i/o 100 - i/o 104 i/o 105 - i/o 109 i/o 110 - i/o 114 i/o 115 - i/o 119 i/o 120 - i/o 124 i/o 125 - i/o 127 29, 35, 40, 46, 52, 57, 62, 68, 74, 79, 85, 90, 96, 110, 116, 121, 127, 133, 138, 144, 149, 155, 160, 6, 13, 30, 36, 41, 47, 53, 58, 64, 69, 75, 80, 86, 92, 105, 112, 117, 122, 128, 134, 139, 145, 150, 156, 2, 7, 14, global output enable input pins. goe 0, goe 1 20 reset y0, y1, y2 21 ispen 22 sdi/in 7 2 23 sclk/in 0 2 24 mode/in 1 2 104 sdo/in 6 2 output/input - this pin performs two functions. when ispen is logic low, it functions as the pin to read the isp data. when ispen is high, it functions as a dedicated input pin. input - this pin performs two functions. when ispen is logic low, it functions as pin to control the operation of the isp state machine. when ispen is high, it functions as a dedicated input pin. input - this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. when ispen is high, it functions as a dedicated input pin. ground (gnd) 1, 81, 10, 107, 27, 125, 18, 19, 101 100, 99, gnd 45, 143 97, 98, 102, 103 63, v (+5v) 12, 111, 31, 131, 51, 151 vcc 71, 91, tqfp pin numbers 27, 35, 41, 46, 52, 59, 65, 71, 77, 83, 90, 95, 102, 116, 124, 130, 135, 141, 148, 154, 160, 167, 173, 3, 8, 16, 28, 36, 42, 47, 53, 60, 66, 72, 79, 85, 91, 96, 103, 119, 125, 131, 136, 143, 149, 155, 161, 168, 174, 4, 9, 17, 31, 37, 43, 48, 55, 61, 67, 73, 80, 86, 92, 97, 104, 120, 126, 132, 138, 145, 150, 156, 163, 169, 175, 5, 12, 18 32, 38, 44, 50, 57, 62, 68, 75, 81, 87, 93, 99, 105, 121, 127, 133, 139, 146, 151, 158, 164, 170, 176, 6, 14, 33, 39, 45, 51, 58, 63, 70, 76, 82, 88, 94, 101, 115, 123, 129, 134, 140, 147, 153, 159, 165, 171, 2, 7, 15, 22 23 24 25 26 114 1, 89, 11, 117, 29, 137, 19, 21, 111 110, 109, 49, 157 106, 107, 112, 113 69, 13, 122, 34, 144, 56, 166 78, 100, cc no connect. nc 1 20, 74, 128, 30, 84, 142, 40, 98, 152, 54, 108, 162, 64, 118 172 dedicated input pins to the device. in 2 - in 5 select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 10 use isplsi 2128e for new designs pin configuration isplsi 2128/a 160-pin pqfp pinout diagram isplsi 2128/a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 gnd i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 gnd i/o 122 vcc i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 y0 y1 reset ispen 1 sdi/in 7 1 sclk/in 0 1 mode/in 1 i/o 0 i/o 1 gnd i/o 2 i/o 3 i/o 4 vcc i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 113 i/o 112 i/o 111 i/o 110 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 vcc i/o 104 i/o 103 i/o 102 i/o 101 i/o 100 i/o 99 i/o 98 gnd i/o 97 i/o 96 i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 vcc i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 gnd i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 vcc i/o 68 i/o 67 i/o 66 gnd i/o 65 i/o 64 sdo/in 6 1 in 5 in 4 y2 goe 0 goe 1 in 3 in 2 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 vcc i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 gnd i/o 14 i/o 15 i/o 16 i/o 17 gnd i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 vcc i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 gnd i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 vcc i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 1. pins have dual function capability. 160-pqfp/2128a select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 11 use isplsi 2128e for new designs isplsi 2128/a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 gnd i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 1 nc gnd i/o 122 vcc i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 y0 1 nc y1 reset ispen 2 sdi/in 7 2 sclk/in 0 2 mode/in 1 i/o 0 i/o 1 gnd 1 nc i/o 2 i/o 3 i/o 4 vcc i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 1 nc i/o 10 i/o 11 i/o 12 i/o 13 i/o 113 i/o 112 i/o 111 i/o 110 nc 1 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 vcc i/o 104 i/o 103 i/o 102 nc 1 i/o 101 i/o 100 i/o 99 i/o 98 gnd i/o 97 i/o 96 i/o 95 i/o 94 nc 1 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 vcc i/o 86 nc 1 i/o 85 i/o 84 i/o 83 i/o 82 gnd i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 nc 1 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 vcc i/o 68 i/o 67 i/o 66 nc 1 gnd i/o 65 i/o 64 sdo/in 6 2 in 5 in 4 y2 goe 0 goe 1 nc 1 in 3 in 2 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 vcc i/o 58 nc 1 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 gnd i/o 14 i/o 15 i/o 16 i/o 17 gnd i/o 18 i/o 19 i/o 20 i/o 21 1 nc i/o 22 vcc i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 1 nc i/o 30 i/o 31 i/o 32 i/o 33 gnd i/o 34 i/o 35 i/o 36 i/o 37 1 nc i/o 38 i/o 39 i/o 40 vcc i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 1 nc i/o 46 i/o 47 i/o 48 i/o 49 176-tqfp/2128a 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability. pin configuration isplsi 2128/a 176-pin tqfp pinout diagram select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 12 use isplsi 2128e for new designs part number description isplsi 2128/a ordering information conventional packaging device number 2128 1 2128a 1. discontinued per pcn #02-06. contact rochester electronics for available inventory. isplsi xxxxx xxx x x grade blank = commercial i = industrial x speed 100 = 100 mhz f max 80 = 81 mhz f max power l = low package q = pqfp device family m = mqfp t = tqfp qn = lead-free pqfp tn = lead-free tqfp laicremmoc ylima f) zhm(xam f) sn(dp tr ebmungniredr oe gakcap islpsi 00 10 1p fqpnip-061 00 10 1p fqtnip-671 1 85 1p fqpnip-061 1 85 1 isplsi 2128a-100lq160 isplsi 2128a-100lt176 isplsi 2128a-80lq160 isplsi 2128a-80lt176 pfqtnip-671 00 10 1p fqpnip-061 00 10 1p fqtnip-671 1 85 1p fqpnip-061 1 85 1 isplsi 2128-100lq 1 isplsi 2128-100lt 1 isplsi 2128-80lq 1 isplsi 2128-80lt 1 pfqtnip-671 1. discontinued per pcn #02-06. contact rochester electronics for available inventory. lairtsudni ylima f) zhm(xam f) sn(dp tr ebmungniredr oe gakcap islpsi 1 85 1p fqtnip-671 1 85 1p fqtnip-671 isplsi 2128a-80lt176i isplsi 2128-80lti 1 1. discontinued per pcn #02-06. contact rochester electronics for available inventory. select devices have been discontinued. see ordering information section for product status.
specifications isplsi 2128/a 13 use isplsi 2128e for new designs isplsi 2128/a ordering information (cont.) lead-free packaging revision history laicremmoc ylima f) zhm(xam f) sn(dp tr ebmungniredr oe gakcap islpsi 00 10 1 lead-free 160-pin pqfp lead-free 176-pin tqfp lead-free 176-pin tqfp lead-free 160-pin pqfp 00 10 1 1 85 1 1 85 1 isplsi 2128a-100lqn160 isplsi 2128a-100ltn176 isplsi 2128a-80lqn160 isplsi 2128a-80ltn176 lairtsudni ylima f) zhm(xam f) sn(dp tr ebmungniredr oe gakcap islpsi 1 85 1 isplsi 2128a-80ltn176i lead-free 160-pin tqfp date version 10 09 august 2006 change summary updated for lead-free package options. previous lattice release. select devices have been discontinued. see ordering information section for product status.

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